Integrated circuit (IC) devices manufactured today generally rely upon an elaborate system of conductive interconnects for wiring together transistors, resistors, and other IC components which are formed on a semiconductor substrate. The technology for forming these interconnects is highly sophisticated and well understood by practitioners skilled in the art. In a typical IC device manufacturing process, many layers of interconnects are formed over a semiconductor substrate, each layer being electrically insulated from adjacent layers by an interposing dielectric layer. It is extremely important that the surface of these interposing dielectric layers be as flat, or planar, as possible to avoid problems associated with optical imaging and step coverage which could frustrate the proper formation and performance of the interconnects.
As a result, many planarization technologies have evolved to support the IC device manufacturing industry. One such technology is called chemical mechanical polishing or planarization (CMP). CMP includes the use of lapping machines and other chemical mechanical planarization processes to smooth the surface of a layer, such as a dielectric layer, to form a planar surface. This is achieved by rubbing the surface with an abrasive material, such as a polishing pad, to physically etch away rough features of the surface, much in the same way sandpaper smoothes the surface of wood. Rubbing of the surface may be performed in the presence of certain chemicals which may be capable of chemically etching the surface as well. After a dielectric layer has been sufficiently smoothed using CMP, interconnects may be accurately and reliably formed on the resulting planar surface.
FIG. 1a illustrates a semiconductor substrate 10 upon which a layer of interconnects 11 has been formed. A dielectric layer 12 is deposited over the surface of interconnects 11. Note how the surface of dielectric layer 12 has conformed to the underlying topography of interconnects 11, resulting in the non-planar surface illustrated. FIG. 1b illustrates the substrate of FIG. 1a after CMP is used to polish back the surface of dielectric layer 12 to the surface of interconnects 11, planarizing the substrate. Another dielectric layer may be deposited on the flat surface of the substrate of FIG. 1b to form a flat dielectric surface upon which another interconnect layer may be formed.
A concern in CMP is how to etch a sufficient amount of material to provide a smooth surface without removing an excessive amount of the important, underlying materials. For example, if the CMP process used to form the substrate illustrated in FIG. 1b does not stop on the surface of interconnects 11, all or a portion of interconnects 11 may be etched away, destroying or at least hindering the operation of the resulting IC device. Therefore, a precise etch endpoint detection technique is needed for indicating when the CMP process has sufficiently planarized the surface of a substrate and should be stopped to prevent over-etching any underlying materials.
One method for endpoint detection is simply timing the CMP and halting the process when a predetermined period of time has elapsed. Unfortunately, the etch rates of similar substrates differ significantly depending on how worn-out the abrasive polishing pad becomes over time. Even if the polishing pad is continually reconditioned, consistent etch rates are difficult to maintain.
Another method for endpoint detection involves capacitive measurement of the dielectric film undergoing CMP, and using these measurements to determine the thickness of the dielectric film during etch. Once a predetermined thickness of the dielectric film is reached, the CMP process is halted. While this endpoint detection method overcomes the problems associated with shifting etch rates, the method is frustrated by the formation of multiple patterned layers on the semiconductor substrate. In addition, the method is only applicable to CMP of dielectric layers and is inadequate for damascene processes in which conductive layers are polished by CMP to form interconnects.
Another method for endpoint detection involves sensing the change in friction between CMP of the material being polished and the underlying material called a stopping layer. Once a change in friction is detected, indicating the stopping layer has been reached, the process is halted. This method is only effective if the coefficient of friction between the material being polished is different from the underlying material. Therefore, this method is wholly inadequate for planarizing dielectric layers to a consistent thickness in the process illustrated in FIGS. 2a and 2b.
FIG. 2a illustrates a semiconductor substrate 20 upon which a layer of interconnects 21 has been formed. A thick dielectric layer 22 is deposited over the substrate. FIG. 2b illustrates the substrate of FIG. 2a after the upper portion of dielectric layer 22 is planarized by CMP. Note that in this interlayer dielectric process, there is no underlying layer upon which a change in friction may be sensed. The CMP process is stoped midway through dielectric layer 22. Therefore, the method of endpointing a CMP process by detecting a change in friction between differing films would not work in this case.
A method for endpointing a CMP process is desired which accounts for shifting etch rates, can be performed on any material at any layer of the device, and doesn't rely on an underlying stopping layer.